The present invention is directed to integrated circuits. More particularly, the invention provides level shifting for voltage drivers. Merely by way of example, the invention has been applied to half-bridge or full-bridge topologies (e.g., LLC resonant topologies). But it would be recognized that the invention has a much broader range of applicability.
Switch-mode power supplies have been developed and used for low-power applications as well as high-power applications. Power-supply chips that often are highly integrated usually need to accommodate both high-voltage usage and low-voltage usage, which may involve many issues, such as voltage tolerance, noise, speed, and parasitics. Challenges remain to develop proper interface circuits for both high-voltage signals and low-voltage signals. For example, for normal circuit operations, voltages applied on devices usually need to be kept within a certain range. As another example, signals often need to be transmitted quickly while signal accuracy needs to be maintained. In yet another example, power consumption and heat generation of a switch-mode power supply usually needs to be reduced, and efficiency of the power supply needs to be improved. In yet another example, satisfactory performance of electrostatic-discharge (ESD) is often needed.
To improve integration of the power-supply chips and reduce costs and power consumption, control circuits of the power-supply chips usually are kept at a low voltage (e.g., 5-6 V). Output circuits of the power-supply chips (e.g., gate drivers), such as certain half-bridge high-side level-shift and gate driver components, often generate a high output voltage (e.g., several hundred volts).
FIG. 1 is a simplified conventional diagram showing a system with level shifting for controlling switches. The system 100 includes a signal generator 102, a high-side level-shift and gate driver component 104, a low-side gate driver 106, two switches 108 and 110, a capacitor 112, a diode 114 and an inductor 116.
For example, the switch 108 is a metal-oxide-semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). In another example, the switch 110 is a metal-oxide-semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). In yet another example, the signal generator 102 generates pulse-width-modulation (PWM) signals.
The low-side gate driver 106 receives a low-side voltage 126 (e.g., vddl) and a reference voltage 128 (e.g., GND). A voltage signal 137 (e.g., VREG) is received at the diode 114 which generates a voltage 130 (e.g., vddh). The high-side level-shift and gate driver component 104 receives the high-side voltage 130 (e.g., vddh) and a high-side floating voltage 132. The switches 108 and 110 receive an input voltage 136 (e.g., Vin) and the reference voltage 128. For example, the high-side floating voltage 132 is associated with a half-bridge node 134 (e.g., HB). In yet another example, the reference voltage 128 (e.g., GND) is a ground voltage (e.g., 0V). In yet another example, the magnitude of the voltage signal 137 (e.g., VREG) is in the range of 10 V to 20 V. In yet another example, the input voltage 136 (e.g., Vin) is up to 400 V. In yet another example, the high-side floating voltage 132 changes (e.g., between 0 V and the input voltage 136) based on the status of the switches 108 and 110 and the system 100. In yet another example, the high-side voltage 130 (e.g., vddh) is higher than the high-side floating voltage 132, and the difference between the high-side voltage 130 (e.g., vddh) and the high-side floating voltage 132 is approximately equal to the voltage signal 137 (e.g., VREG) minus a forward voltage of the diode 114 in magnitude.
In operation, the signal generator 102 generates a high-side modulation signal 118 (e.g., PWM_H) and a low-side modulation signal 120 (e.g., PWM_L). The high-side level-shift and gate driver component 104 receives the high-side modulation signal 118 and in response generates a high-side gate-drive signal 122 (e.g., GATE_HV) to drive the switch 108. The low-side gate driver 106 receives the low-side modulation signal 120 and in response generates a low-side gate-drive signal 124 (e.g., GATEL) to drive the switch 110.
FIG. 2 is a simplified conventional diagram showing certain components of the high-side level-shift and gate driver component 104 as part of the system 100. The high-side level-shift and gate driver component 104 includes a pulse generator 202, a level-shift circuit 204, and a high-side gate driver 298. The level-shift circuit 204 includes two transistors 206 and 208, four resistors 210, 212, 214 and 216, two Zener diodes 218 and 220, two inverters 222 and 224, and a flip-flop 226. For example, the transistor 206 includes a parasitic capacitor 228, and the transistor 208 includes a parasitic capacitor 230. In another example, the transistors 206 and 208 are both N-channel MOSFETs.
The transistors 206 and 208 can sustain high drain-source voltages. The resistors 214 and 216 are used to limit the maximum currents that flow through the transistors 206 and 208, respectively. The resistors 210 and 212 are used to set the initial status of the level-shift circuit 204. The Zener diodes 218 and 220 are used to set minimum values of signals 240 (e.g., setb) and 246 (e.g., resetb) to a floating voltage 242 (e.g., HB), respectively.
In operation, the pulse generator 202 receives a modulation signal 232 (e.g., PWM_H as shown by a waveform 256). For example, the pulse generator 202, in response, generates a pulse signal 234 (e.g., set) at a rising edge of the modulation signal 232 (e.g., as shown by a waveform 258). The pulse generator 202 also generates a pulse signal 236 (e.g., reset) at a falling edge of the modulation signal 232 (e.g., as shown by a waveform 260).
If the transistor 206 is turned on by the pulse signal 234 (e.g., set), a current 238 flows through the transistor 206 (e.g., HVNM1) and the resistor 214 (e.g., Rdn). For example, a maximum value of the current 238 is determined based on the level of the pulse signal 234 and the resistance of the resistor 214. If a voltage generated at the resistor 210 (e.g., Rup) is larger than a breakdown voltage of the Zener diode 218, a large portion of the current 238 flows through the Zener diode 218. If the resistance of the resistor 210 is large enough, a small portion of the current 238 flows through the resistor 210. Once the Zener diode 218 breaks down, the signal 240 (e.g., setb) is close to the floating voltage 242. The inverter 222, in response, generates a signal 248 (e.g., at a logic high level) when the signal 240 falls below a threshold level of the inverter 222. When the transistor 206 is turned on by the pulse signal 234 (e.g., set), the transistor 208 (e.g., HVNM2) is off as the pulse signal 236 (e.g., reset) is at a logic low level. The signal 246 (e.g., resetb) is close to a voltage 244 (e.g., vddh). The inverter 224 generates a signal 250 (e.g., at the logic low level). The flip-flop 226 receives the signals 248 and 250, and generates a pre-gate-drive signal 252 (e.g., at the logic high level). The high-side gate driver 298 receives the pre-gate-drive signal 252 and outputs a gate drive signal 299 (e.g., GATE_HV). For example, the signal 240 (e.g., setb) and the signal 246 (e.g., resetb) each vary from the input voltage 136 (e.g., Vin) to the sum of the input voltage 136 and the voltage signal 137 (e.g., VREG) of FIG. 1. As another example, the signal 240 (e.g., setb) and the signal 246 (e.g., resetb) vary from 400 V to 411 V.
If the transistor 208 is turned on by the pulse signal 236 (e.g., reset), a current 254 flows through the transistor 208 and the resistor 216 (e.g., Rdn). For example, a maximum value of the current 254 is determined based on the level of the pulse signal 236 and the resistance of the resistor 216. If a voltage generated at the resistor 212 (e.g., Rup) is larger than a breakdown voltage of the Zener diode 220, a large portion of the current 254 flows through the Zener diode 220. If the resistance of the resistor 212 is large enough, a small portion of the current 254 flows through the resistor 212. Once the Zener diode 220 breaks down, the signal 246 (e.g., resetb) is close to the floating voltage 242. The inverter 224, in response, generates the signal 250 (e.g., at the logic high level) when the signal 246 falls below a threshold level of the inverter 224. When the transistor 208 is turned on by the pulse signal 236 (e.g., reset), the transistor 206 is off as the pulse signal 234 (e.g., set) is at the logic low level. The signal 240 (e.g., setb) is close to the voltage 244 (e.g., vddh). The inverter 222 generates the signal 248 (e.g., at the logic low level). The flip-flop 226 receives the signals 248 and 250, and generates the pre-gate-drive signal 252 (e.g., at the logic low level) that is received by the high-side gate driver 298.
For example, the maximum value of the current 238 that flows through the transistor 206 is often reduced by increasing the resistance of the resistor 214 in order to reduce power consumption and avoid damaging the transistor 206. In another example, the maximum value of the current 254 that flows through the transistor 208 is often reduced by increasing the resistance of the resistor 216.
But the level-shift circuit 204 has certain disadvantages. It is usually hard to optimize the resistance of Rup (e.g., the resistor 210 or the resistor 212) and Rd, (e.g., the resistor 214 or the resistor 216). On one hand, it is often desirable to have Rup much larger than Rdn to increase the turn-on speed of the level-shift circuit 204. For example, the resistor 210 (e.g., Rup) usually has a much larger resistance than the resistor 214 (e.g., Rdn), so that when the transistor 206 is turned on, a source current of the transistor 206 that flows through the resistor 210 is much smaller than a sink current of the transistor 206 that flows through the resistor 214 in magnitude. On the other hand, to avoid logic errors, the signal 240 (e.g., setb) or the signal 246 (e.g., resetb) often needs to change swiftly to the voltage 244 (e.g., vddh) after the pulse signal 234 (e.g., set) or the pulse signal 236 (e.g., reset) passes, respectively. For example, the resistance of the resistor 210 (e.g., Rup) usually needs to be reduced to increase the source current of the transistor 206. In another example, the resistor 214 (e.g., Rdn) often has a large resistance to limit a maximum current of the transistor 206 when the transistor 206 is turned on, and it is hard to choose a small resistance for the resistor 210 (e.g., Rup). Thus, the response speed of the level-shift circuit 204 is usually affected in certain high-frequency applications.
In addition, whether the level-shift circuit 204 can be turned on successfully for a first time often depends on the resistance of Rup (e.g., the resistor 210 or the resistor 212) and Rdn (e.g., the resistor 214 or the resistor 216). The first-time turn-on of the level-shift circuit 204 is usually a hard-switching operation. For example, before the level-shift circuit 204 is turned on for the first time, the floating voltage 242 is about 0 V, and the voltage 244 (e.g., vddh) is about 10 V. In another example, the turn-on resistance of the transistors 206 and 208 is about several kOhms. If the resistance of the resistor 210 (e.g., Rup) is small and the resistance of the resistor 214 (e.g., Rdn) is large, it is often hard to change the signal 240 (e.g., setb) below a logic low level recognizable by the following logic circuits (e.g., the inverter 222), and in turn output the signal 252 above the logic high level.
Further, the transistors 206 (e.g., HVNM1) and 208 (HVNM2) have large parasitic capacitances (e.g., the parasitic capacitors 228 and 230), respectively. For example, in certain soft-switching applications, the pulse signal 234 (e.g., set) arrives after the floating voltage 242 (e.g., HB) and the voltage 244 (e.g., vddh) increase to predetermined voltages, respectively (e.g., from 0 V to 400 V in 200 ns). In another example, during the process of the floating voltage 242 (e.g., HB) and the voltage 244 (e.g., vddh) increasing in magnitude, a charging current 262 is generated through the parasitic capacitor 228 and can be determined based on the following equation.Iramp=Cp×dV/dt  (Equation 1)where Iramp represents the charging current 262, Cp represents the capacitance of the capacitor 228, and dV/dt represents the changing speed of the floating voltage 242 (e.g., HB). For example, if Cp is equal to 5 pF, and dV/dt is equal to 400V/200 ns, the charging current 262 is about 10 mA. In another example, the voltage drop on the resistor 210 (e.g., Rup) generated by the charging current 262 is large enough to break down the Zener diode 218, and cause logic errors.
As another example, in some soft-switching applications (e.g., applications of half-bridge gate drivers of series-parallel resonant converters (SPRC) or LLC resonant converters), the pulse signal 234 (e.g., set) arrives during the process of the floating voltage 242 and the voltage 244 (e.g., vddh) increasing in magnitude. But if the charging current 262 and a charging current 264 that is generated at the capacitor 230 break down the Zener diodes 218 and 220, respectively, the signal 240 (e.g., setb) and the signal 246 (e.g., resetb) are both close to the floating voltage 242. The level-shift circuit 204 may not output the signal 252 at the logic high level in response to the pulse signal 234 (e.g., set).
Moreover, the floating voltage 242 often changes from a low voltage (e.g., close to the ground voltage 266) to a high voltage (e.g., 400 V or higher). The level-shift circuit 204 usually is isolated from a die substrate in a high-voltage (e.g., greater than 500 V) isolation process that is often very expensive. A die is a block of semiconductor material, on which a functional circuit is fabricated.
FIG. 3(a) is a simplified conventional diagram showing another system with level shifting for controlling switches. The system 300 includes a signal generator 302, a high-side level-shift and gate driver component 304, a low-side gate driver 306, two switches 308 and 310, a capacitor 312, a diode 314 and an inductor 316. The signal generator 302, the high-side level-shift and gate driver component 304, and the low-side gate driver 306 are integrated into a single die 340. For example, the system 300 is the same as the system 100. A high-voltage (e.g., greater than 500 V) isolation process is often needed to manufacture the system 300. For example, certain sub-components of the high-side level-shift and gate driver component 304 need to be isolated from the silicon substrate by at least 500 volts, resulting in very high manufacturing costs.
FIG. 3(b) is a simplified conventional diagram showing yet another system with level shifting for controlling switches. The system 350 includes a signal generator 352, a high-side level-shift and gate driver component 354, a low-side gate driver 356, two switches 358 and 360, a capacitor 362, a diode 364 and an inductor 366. The signal generator 352 and the low-side gate driver 356 are integrated into a die 370. The high-side level-shift and gate driver component 354 is integrated into another die 372. The dies 370 and 372 are packaged into a chip. For example, the system 350 is the same as the system 100. A bonding wire 374 connects the dies 370 and 372 for signal transmission. For example, a high-side modulation signal 368 (e.g., PWM_H) generated by the signal generator 352 is output from the die 370 via the wire 374 to the die 372 at a terminal 376 (e.g., PWM_IN). Usually, an expensive high-voltage (e.g., greater than 500 V) isolation process is still needed for manufacturing the system 350, even though the manufacturing cost of the system 350 is often less than that of the system 300.
Hence it is highly desirable to improve the techniques of level shifting for high voltage drivers.